This post this Part 5 in the Multi part Series of the , Part 1 we Compared sensor, Part 2 was Hardware and Mechanical Design, Part 3 about Sensor Solution, Part 4 About Software Arch, This Part 5 is going in details about FPGA/PL Pipeline. This Part primarily focus how FPGA PL ISP Blocks is implemented where boundary between PL modules are defined.
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| CHC5 ISP |
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| Most Basic FPGA Pipeline |
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| CHC5 Advance Custom Pipeline Full Optmized |
Capture front end
MIPI D-PHY receiver - Xilinx D-PHY primitive, 4 data lanes at 1250 Mbps.
Converts the sensor's serial MIPI electrical signalling into the parallel PPI byte interface for the CSI-2 receiver.
CHC5 CSI-2 receiver - the in-house CSI-2 parses lanes into packets and ECC/CRC-checks them.
Emits the RAW Bayer AXI-Stream video plus error/status registers; programmed by kernel driver.
RAW-domain ISP (Bayer)
Black-level corrector - Performs Black Level Correction the programmed sensor pedestal from RAW pixel.
3A statistics engine - 16x16 zone accumulator grid plus histogram, memory-mapped in the register family.
AWB Block - per channel digital gain multiplier in the RAW domain to perform WB correction.
This is where AWB corrections are physically applied, before demosaic.
Demosaic - the in-house Bayer-to-RGB interpolator.
Turns the single-channel CFA stream into full 3-channel RGB; its line buffers set the pipeline latency.
RGB/YUV-domain ISP
Colour-correction matrix (CCM) - 3x3 matrix with offsets, loaded per sensor from the manifest tuning. Corrects sensor spectral crosstalk into colorimetric RGB; part of 3A chain.
Gamma LUT - programmable per-channel gamma table (the custom core from stage 13). Applies the encoding curve so 8-bit and YUV/HDMI outputs aren't linear-dark.
RGB-to-YUV converter (CSC) - custom RGB to YUV 4:2:2 converter with chroma filtering. Produces the stream used by YUV and Mono output formats and the HDMI preview.
USB output leg (FX3 GPIF)
USB elastic FIFO - buffering between the packer and the GPIF clock domain / FX3 backpressure.
GPIF width funnel (down to 32-bit) - narrows the packed stream to the GPIF bus width. Drives the top-level GPIF data/clock/LSYNC/FSYNC pins into the FX3.
GigE output leg (GVSP via DDR)
GigE frame DMA - lands packed frames into DDR ring buffers. The gvsp kernel driver harvests them and streams GVSP packets out of the GEM.
HDMI preview leg
Stream-to-video bridge (Xilinx v_axi4s_vid_out) - turns the AXI-Stream preview into parallel video with syncs, locked to the timing generator. Also handles the crossing into the 148.5 MHz pixel-clock domain.
Video timing generator (Xilinx VTC) - generates the fixed HDMI sync/blanking timing the bridge locks to.
HDMI/DVI encoder - serialises parallel RGB plus syncs into TMDS for the HDMI connector.
Trigger and auxiliary I/O
Camera I/O and sync block - aux-I/O core: opto in/out, xtrig1/2, xmaster, XHS/XVS and strobe pins at the top level.
Infrastructure
Zynq processing system - the ARM cores running Linux, the DDR controller, GEM Ethernet, and the GP/HP AXI ports everything hangs off.
Source of the 100 MHz fabric reference and the HP slave ports both DMAs write through.
ISP Specification
Full fledged ISP All Standard and Enhance Features Dedicated handling of Color and Mono Sensors.
ISP Specifications
- Camera ISP on FPGA Logic
- Black Level Correction
- Demosaic
- 3A Engine
- Auto White Balance
- Auto Exposure
- Auto Focus
- Auto Gain
- Color Space Conversion
- Gamma Correction
- Video Processing for HDMI
- Dedicated USB , Ethernet and HDMI Pipeline
- Simultaneous USB , Ethernet and HDMI operation
- Dedicated GigE Vision, USB3 Vision, UVC and HDMI Pipeline
- Frame Rate Conversion Specifically for HDMI
- Supports 1 to 4 Pixel Per Clock
- 150Mhz Video Pipeline Clock
- Virtually no frame rate limit
- 600 Mpixel/second ISP processing rate at 4PPC and 1200Mpixel/second at 8PPC
- ISP max 4PPC:
- 640×480 ~2000 FPS
- 1080p ~170 FPS
- 4K ~40 FPS
- ISP max 8PPC:
- 640×480 ~4000 FPS
- 1080p ~340 FPS
- 4K ~80 FPS
Supported Sensor Specs
- Sensors : Supports all Sensor that meets Sensor Specs
- Interface : All MIPI D-PHY/LVDS/Sub LVDS/Low Voltage LVDS/SLVS Sensors
- Resolution : ~128Mpixel Max, No Min limit
- Shutter : Global or Rolling Shutter
- Number of Data Lanes : upto 8 Lanes, 4 Lanes x1ch or 4Lane x2ch
- Number of Sensors: 2 (4 Lanes), 3 (2 Lanes)
- Max Data rate : 1.25Gbps/Lane, max 10Gbps with 8Lanes
- Pixel format: RAW8, RAW12, RAW14 , PWL HDR
- Freely user configurable Frame rate
- Frame rate is sensor and Streaming Interface Dependent
- Frame rate Details provided in individual Sensor specs
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