This post this Part 5 in the Multi part Series of the , Part 1 we Compared sensor, Part 2 was Hardware and Mechanical Design, Part 3 about Sensor Solution,  Part 4  About Software Arch, This Part 5 is going in details about FPGA/PL Pipeline. This Part primarily focus how FPGA PL ISP Blocks is implemented where boundary between PL modules are defined. CHC5 ISP      Launching September 1st Week Most Basic FPGA Pipeline  CHC5 Advance Custom Pipeline Full Optmized Capture front end MIPI D-PHY receiver - Xilinx D-PHY primitive, 4 data lanes at 1250 Mbps. Converts the sensor's serial MIPI electrical signalling into the parallel PPI byte interface for the CSI-2 receiver. CHC5 CSI-2 receiver - the in-house CSI-2 parses lanes into packets and ECC/CRC-checks them. Emits the RAW Bayer AXI-Stream video plus error/status registers; programmed by kernel driver. RAW-domain ISP (Bayer) Black-level corrector - Performs Black Level Correction the programmed sensor pedesta...