This post is going to be about Breakout board PCB for FMC Connector which are widely used on Xilinx High End FPGA board. LPC Low pinout connections do not have any GTY or GTH or GTX or MGT connections they have only differential normal SerDes connections ANSI/VITA 57.1 compliant
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Schematic has only 4 LPC rows connected directly to Top layer and board layer connector. 1.27 mm Header route out all connections including GND pins all the Signals are routed in Differential connection
PCB
Signal Rows in FMC LPC vs. HPC Connector pins Difference
Row | LPC (160 Pins) | HPC (400 Pins) | Function |
---|---|---|---|
A | ❌ No | ✅ Yes | Power, control, & reference clocks |
B | ❌ No | ✅ Yes | Additional I/O and clocks |
C | ✅ Yes | ✅ Yes | Single-ended I/O & differential pairs |
D | ✅ Yes | ✅ Yes | More I/O & differential pairs |
E | ❌ No | ✅ Yes | Additional differential pairs (DP0-9) |
F | ❌ No | ✅ Yes | More differential pairs (DP10-17) |
G | ✅ Yes | ✅ Yes | Primary differential pairs & clocks |
H | ✅ Yes | ✅ Yes | More primary differential pairs & clocks |
J | ❌ No | ✅ Yes | Gigabit transceiver signals (MGTs) |
K | ❌ No | ✅ Yes | More MGTs & ground |
EEPROM Content
Thank you, Gaurav, for this and other open source work! Very through explanations and professional descriptions, clearly stated. Excellent.
ReplyDeleteMy Cadence translator seems unable to import this claiming "FMC_HPC_LPC_Signals.SchDoc is not ASCII". Can your repost on github, please?
ReplyDelete(Same for pcbDoc file.)
ReplyDelete