FPGA FMC Breakout Board for Accessing LPC Connections from High End Xilinx FPGA Ultrascale+ Zynq

This post is going to be about Breakout board PCB for FMC Connector which are widely used on Xilinx High End FPGA board. LPC Low pinout connections do not have any GTY or GTH or GTX or MGT connections they have only differential normal SerDes connections ANSI/VITA 57.1 compliant








YouTube 






Schematic 

Schematic has only 4 LPC rows connected directly to Top layer and board layer connector. 1.27 mm Header route out all connections including GND pins all the Signals are routed in Differential connection 


PCB










Signal Rows in FMC LPC vs. HPC Connector pins Difference

RowLPC (160 Pins)HPC (400 Pins)Function
A❌ No✅ YesPower, control, & reference clocks
B❌ No✅ YesAdditional I/O and clocks
C✅ Yes✅ YesSingle-ended I/O & differential pairs
D✅ Yes✅ YesMore I/O & differential pairs
E❌ No✅ YesAdditional differential pairs (DP0-9)
F❌ No✅ YesMore differential pairs (DP10-17)
G✅ Yes✅ YesPrimary differential pairs & clocks
H✅ Yes✅ YesMore primary differential pairs & clocks
J❌ No✅ YesGigabit transceiver signals (MGTs)
K❌ No✅ YesMore MGTs & ground



EEPROM Content 






Comments

  1. Thank you, Gaurav, for this and other open source work! Very through explanations and professional descriptions, clearly stated. Excellent.

    ReplyDelete
  2. My Cadence translator seems unable to import this claiming "FMC_HPC_LPC_Signals.SchDoc is not ASCII". Can your repost on github, please?

    ReplyDelete

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