FPGA FMC NVMe Drive SSD, NVMe SSD Drive on PCIe M.2 Adapter FMC HPC FPGA

As I am working with more High end FPGA boards. I need more different type of peripheral pugged into my FPGA board with FMC connector. This board is going to about Why and how i designed FMC HPC PCIe M.2 carrier adapter card so that You can Plug NVMe SSD Drive or any other PCIe Peripheral in M.2 Form factor. 

As case with most modern FPGA board. They come with High density high speed expansion connector. Out of which FMC connectors are most common. FMC Connectors also  have few types, There FMC HPC connector which has all the pins of HPC connector , While there is a FMC LPC connector which has only a subset of HPC connector. Both FMC HPC and LPC connectors are basically same in terms of mechanical dimensions, They both fit into one another. Its just LPC has few electrical pins. The there is also a even bigger connector even with more pins called Vita 57.4 FMC+ , it is mostly Common with very expensive high end boards. 


As I was working on my camera project i needed very fast storage for my FPGA, Where I could store RAW or even Compressed Video from Camera. This Little Board that I designed will allow you Connect very Fast NVMe SSD storage to your FPGA board. This board can Carry Two NVMe SSD  Connected to FPGA. Both devices can be operated parallelly on full x4 PCIe link . This FPGADrive solution give you Multigigabyte per second performance. Allowing to work for any application.


Features

  • FPGA FMC HPC M.2 Carrier board for  NVMe SSD M.2 M Key and Other M.2 m-key card, such as WiFi for AI Accelerator
  • PCIe Gen4 X4 on both of the slots 
  • High Quality 8 Layer Board with Controlled Stripline routing.
  • Independently Power both both Slots Allow Full potential. 
  • Two M Key slots with 4 Different Sizes.
  • Supports 2280, 2260, 2242, 2230 M.2 Sizes.
  • Power and Activity LED indication 
  • Supported by All Xilinx boards with Fully HPC connectors.
  • FMC HPC ANSI/VITA 57.1 compliant.
  • Board is VITA57.1 Compliant Has EEPROM to Configure voltages to support High end FPGA VADJ
YouTube Video


PCB


Vivado Design For PCIe Bridge IP

Project source and example design available on Github 


xdma and very important Reset Signal

Configuring XDMA






Linux Operation

Linux NVMe Driver Config

You need to enable few drivers in linux configuration of ultrascale+ FPGA

PCIe Express Port Bus Support

NVMe Express Block Device Support

Xilinx DMA PL PCIe Host Bridge Support



Device tree

lspci Ouptut showing Both SSD


Gen 4 link speed with SN770M



Benchmark

Write Benchmark Showing Speed of 1.4 GByte/Second

Write Benchmark Showing Speed of 1.4 GByte/Second

Read Bench Mark Showing Speed of 2.5GByte/Second
Read Bench Mark Showing Speed of 2.5GByte/Second




Pin Assignment 

NVMe1 Interface 

FMC Pin FMC Pin Name NVMe Net Name Description ZCU106 HPC0 ZCU106 HPC1
C2 FMC_HPC0_DP0_C2M_P NVMe1_PER0_P PCIe Lane 0 (SSD to FPGA) Positive R6 AJ6
C3 FMC_HPC0_DP0_C2M_N NVMe1_PER0_N PCIe Lane 0 (SSD to FPGA) Negative R5 AJ5
C6 FMC_HPC0_DP0_M2C_P NVMe1_PET0_P PCIe Lane 0 (FPGA to SSD) Positive R2 AK4
C7 FMC_HPC0_DP0_M2C_N NVMe1_PET0_N PCIe Lane 0 (FPGA to SSD) Negative R1 AK3
A22 FMC_HPC0_DP1_C2M_P NVMe1_PER1_P PCIe Lane 1 (SSD to FPGA) Positive T4  
A23 FMC_HPC0_DP1_C2M_N NVMe1_PER1_N PCIe Lane 1 (SSD to FPGA) Negative T3  
A2 FMC_HPC0_DP1_M2C_P NVMe1_PET1_P PCIe Lane 1 (FPGA to SSD) Positive U2  
A3 FMC_HPC0_DP1_M2C_N NVMe1_PET1_N PCIe Lane 1 (FPGA to SSD) Negative U1  
A26 FMC_HPC0_DP2_C2M_P NVMe1_PER2_P PCIe Lane 2 (SSD to FPGA) Positive N6  
A27 FMC_HPC0_DP2_C2M_N NVMe1_PER2_N PCIe Lane 2 (SSD to FPGA) Negative N5  
A6 FMC_HPC0_DP2_M2C_P NVMe1_PET2_P PCIe Lane 2 (FPGA to SSD) Positive P4  
A7 FMC_HPC0_DP2_M2C_N NVMe1_PET2_N PCIe Lane 2 (FPGA to SSD) Negative P3  
A30 FMC_HPC0_DP3_C2M_P NVMe1_PER3_P PCIe Lane 3 (SSD to FPGA) Positive U6  
A31 FMC_HPC0_DP3_C2M_N NVMe1_PER3_N PCIe Lane 3 (SSD to FPGA) Negative U5  
A10 FMC_HPC0_DP3_M2C_P NVMe1_PET3_P PCIe Lane 3 (FPGA to SSD) Positive V4  
A11 FMC_HPC0_DP3_M2C_N NVMe1_PET3_N PCIe Lane 3 (FPGA to SSD) Negative V3  
D4 FMC_HPC0_GBTCLK0_M2C_P FMC_NVMe1_REFCLK_P 100MHz Reference Clock Positive V8 Y8
D5 FMC_HPC0_GBTCLK0_M2C_N FMC_NVMe1_REFCLK_N 100MHz Reference Clock Negative V7 Y7
H22 (Rev D: H19) FMC_HPC0_LA19_P NVMe1_PERST PCIe Fundamental Reset D12 (Rev D: D16) A18
H20 FMC_HPC0_LA15_N NVMe1_PEDET Presence Detect / Interface ID C16 A19
H23 (Rev D: H17) FMC_HPC0_LA19_N NVMe1_DEVSLP Device Sleep / Power Management C11 (Rev D: C16) A21

NVMe2 Interface 

FMC Pin FMC Pin Name NVMe Net Name Description ZCU106 HPC0 ZCU106 HPC1
A34 FMC_HPC0_DP4_C2M_P NVMe2_PER0_P PCIe Lane 0 (SSD to FPGA) Positive H4 X
A35 FMC_HPC0_DP4_C2M_N NVMe2_PER0_N PCIe Lane 0 (SSD to FPGA) Negative H3  
A14 FMC_HPC0_DP4_M2C_P NVMe2_PET0_P PCIe Lane 0 (FPGA to SSD) Positive G2  
A15 FMC_HPC0_DP4_M2C_N NVMe2_PET0_N PCIe Lane 0 (FPGA to SSD) Negative G1  
A38 FMC_HPC0_DP5_C2M_P NVMe2_PER1_P PCIe Lane 1 (SSD to FPGA) Positive L6  
A39 FMC_HPC0_DP5_C2M_N NVMe2_PER1_N PCIe Lane 1 (SSD to FPGA) Negative L5  
A18 FMC_HPC0_DP5_M2C_P NVMe2_PET1_P PCIe Lane 1 (FPGA to SSD) Positive L2  
A19 FMC_HPC0_DP5_M2C_N NVMe2_PET1_N PCIe Lane 1 (FPGA to SSD) Negative L1  
B16 FMC_HPC0_DP6_M2C_P NVMe2_PET2_P PCIe Lane 2 (SSD to FPGA) Positive N2  
B17 FMC_HPC0_DP6_M2C_N NVMe2_PET2_N PCIe Lane 2 (SSD to FPGA) Negative N1  
B36 FMC_HPC0_DP6_C2M_P NVMe2_PER2_P PCIe Lane 2 (FPGA to SSD) Positive M4  
B37 FMC_HPC0_DP6_C2M_N NVMe2_PER2_N PCIe Lane 2 (FPGA to SSD) Negative M3  
B12 FMC_HPC0_DP7_M2C_P NVMe2_PET3_P PCIe Lane 3 (SSD to FPGA) Positive J2  
B13 FMC_HPC0_DP7_M2C_N NVMe2_PET3_N PCIe Lane 3 (SSD to FPGA) Negative J1  
B32 FMC_HPC0_DP7_C2M_P NVMe2_PER3_P PCIe Lane 3 (FPGA to SSD) Positive K4  
B33 FMC_HPC0_DP7_C2M_N NVMe2_PER3_N PCIe Lane 3 (FPGA to SSD) Negative K3  
B20 FMC_HPC0_GBTCLK1_M2C_P FMC_NVMe2_REFCLK_P 100MHz Reference Clock Positive T8  
B21 FMC_HPC0_GBTCLK1_M2C_N FMC_NVMe2_REFCLK_N 100MHz Reference Clock Negative T7  
G9 FMC_HPC0_LA03_P NVMe2_PERST PCIe Fundamental Reset K19  
H7 FMC_HPC0_LA02_P NVMe2_PEDET Presence Detect Signal L20  
G10 FMC_HPC0_LA03_N NVMe2_DEVSLP Device Sleep / Power Management K18  

PCB Image

High Quality 8 Layer PCB with Stripline, Impedance Controlled Routing

Board Image

Board Fits All different Type of M.2 form factors

Threaded Mounting Studs for SSD, Can be Moved Between Positions.


Supported on Wide Varity of FPGA Boards

Supports Stacking of FMC LPC or even HPC Connector who don't Share pins

Standard from factor Allow side by Side Fitting With Other FMC

Top Quality M.2 Connector From TE 

Project source and example design available on Github 


I am an Avionics Engineer, with knowledge of Electronics, Software, FPGA and Embedded Design Engineering.

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