Few day back , I published about atiny little WireFrame FPGA Board, now it is the time to test the weather it is working , and FPGA is getting programmed .this article is goint be very very basic , like how to create xilinx ISE project and write a little binary counter in verilogHDL , how to wireup the module's port to I/O line of the FPGA . and finally implement the module , we will also simmulate the design with the help of verilog Test bench in model sim software.
after getting happy simulation result we will generate programming file(.bit file) and flashing the bit file directly into FPGA with help of a low cost JTAG cable.
we have to implement a module as show in the diagram.
counter.v file , VerilogHDL source file which define the logic behind the module
we will use Behavioural modelling technique,in which you just
have to specify what behaviour you want your module to do .
the tool automatically implements the hardware for job
counter.ucf file, this fill will have mapping information about the FPGA
Hardware pins and the Module ports
that is all you don't need to supply anythig else everything else is done by the tool.
so lets start with the port definition
verilog module port are define defined , like parameter in a c function
for us it will like , we don't need to give exact direction and size here we and put this later on in the module description it self.
|rst, //Reset input|
|clk, //clock output|
|count // count output|
|parameter size = 32;|
|input rst; // reset the counter|
|input clk; // connected to WireFrame on board 25Mhz crystal.|
|output [size-1:0] count; //count is bus with width of size ,which is defined as parameter with value 32|
|always @ (posedge clk) // this always block , runs always on when a positive edge comes on the clock (clk) input|
|if (!rst) // This causes reset counter|
|count = 0;|
|count = count + 1'b1; // if reset is not low then keep incrementing count value at every positive clock edge|
that is all there is nothing else to it. logic part is done now we need to wire these port to the I/O line of FPGA. for that we need to create a .ucf file.
For this particular experiment I am using my WireFrame FPGA Bord. almost any FPGA can be used for this experiment there no such dependency on any specific part, you are free to use any vendor's part ,the verilog code going to be same though the process of implementing the module, working environment and procedure or programming the part is going to be a little different. my board has Xilinx XC3S250E FGPA , the FPGA it self has many I/O line but most of them are used for on board RAM , only 30 I/O line (out which few are only input) are available for use.
we are going to use only 5 I/O line , 3 for counter output and 1 for counter reset input. one more I/O line we need is Clock input but as we have the 25Mhz crystal oscillator on board , it is already connected to I/O pin number 89.
you can chose any I/O line with required capability to use as counter output and reset input , we have made the connection are as following.
port rst at location = P88
port clk at location = P89;
port count bit 2 (MSB) at location = P79;
port count bit 1 Location= P78;
port count bit 0 (LSB at location = P68;
you need to apply requisite power , and connect led to the out pins if you like.
why only 3 bits, 23 ,24,25 are mapped to hardware? it is just a simple little test , we can easily verify the weather the counter is counting with 2-3 output pins , i don't want to mess with many many connection in the hardware, 3 outputs are enough to see if it actually working. and i am very lazy to connect unnecessary hardware to the FPGA.
And i connected 23 , 24 ,25 bits bit of the counter with a simple logic , we have 25Mhz clock input and we wanted to see the binary counter with our counting on led directly with our naked eyes, if you see the a binary counter's behaviour ,next higher significance bit toggle only after the former lesser significance bit toggle twice (because binary number are base of 2) . this can also be said like on every next higher significance bit output the input is divided by 2.
as we have 25Mhz input , on bit 0 of counter output we will get 12.5 Mhz and on bit 1 we will get 6.26Mhz and so on, i can see signal changing this fast with my eyes .so i need to divide this further in the range of less than 10Hz or so.
at bit 23 , which is 24th bit in output starting from bit 0. you got the input clock 25Mhz divided by 2^24 ,output at bit 23 will be 25Mhz/(2^24) = 2.98 Hz , at 24 bit it wil be 0.745 Hz and at bit 25 it will be 0.3275 Hz , we can easily see such a low frequency with led.
Making Port Mapping with ucf file
every single signal in verilog treated as NET ,
so the syntax says NET rst is connected to Location Pin Number 88 and so on .
NET "rst" LOC = P88;
NET "clk" LOC = P89;
NET "count" LOC = P78;
NET "count" LOC = P79;
NET "count" LOC = P68;
as count is an Output , and in verilog you have to define the IO Standard of ever output , as FPGA are capable of many different type of IO Standards like 2.5V CMOS or 3.3V CMOS etc. you need to tell here what exactly you want.
NET "count" IOSTANDARD = LVCMOS33;
NET "count" IOSTANDARD = LVCMOS33;
NET "count" IOSTANDARD = LVCMOS33;
Creating a Project in Xilinx ISE
Xlinux is one of the Major player in FPGA, they provide limited Free Development Environment under the name of Xilinx ISE Design Suite. you can download it from there website and install it into you workstation it is nice and simple , no drama what so ever.
once you launch the ISE Project Navigator , you have to click new project button in the left or in the menu bar , it will look kind of as shown in the image blow
|New project wizard , specify project name|
you have specify the project name and working directory for that project. project name can be any thing.
next step you have to select the target device , as in the demonstration we are working with WireFrame board which has Xilinx XC3S250E, so you chose the family sparten3E and chose the device to be XC3S250E , and you need specify the speed grade of the FPGA also which is -4 at our board , ( you can see marking on the chip)
you need to specify the preferred language to be verilog as we are going to write code in verilogHDL.
that is all just verify setting and finish,
you have got this empty project , now you need to add source file to it , right click on target name in the hierarchy window on the left , then click new source
to add new source you got many options , but you need to add only verilog file for now. select verilog module , specify the name , the name here need a little attention , the verilog file name and module name is always going to be same , the wizard will automatically add the new module with the same name in to newly created verilog file , do not change the name it verilog source ever, if wanted to change module name then need to change the file name also.
if you want you can speicfy all the ports you module going to have , as it will automatically create verilog file for you , but i like it to directly enter in the source so enter nothing and just hit next ,
you have got the editor type your source here , the module source it the real stuff, it actually tells what is need to be done and when , it define all the intelligence the module has.
after entering the module code you need to implement the module and see if it happen successfully , if any error or very serious warning are there then you need to rectify them. to implement right click on the source file , and hit implement top module.
if implementation happen successfully then you have add pin mapping file , this file specify which pin of FPGA is connected to which port of the module, you have to add new source and , select Implementation Constants file. it will be .ucf file. you can automatically create this file with Xilinx pin planner , plan ahead , but for the sake of simplicity lets keep it manual.
we have new .ucf file ender the data here.
To generate programming file , go to design window in the left blow the project hierarchy,and there is a little button in the tree box , which say "Generate Programming files" just click that button , it will happen automatically .
as soon as Programming Files get Generated , the Xilinx ISE will automatically launch ISE iMPACT , Programming Application ,
to Start Programming you first need initilize the JTAG Broundary Scan So that it can detect the FPGA,
So to do that look at the top left corner , in the iMPACT Flows window Right Click on "Boundary Scan" and select initialize Tool chain , The iMPACT will automatically detect the FPGA,
as soon as the FPGA is detected you need to load the .bit file , which is the programming file we just generated in the previous step,
although iMPACT will automatically ask you to provide .bit file , but if it dose not then click on the gren FPGA icon . it will popup a window to select the .bit file.
now you are ready to program just click program button in the left corner , iMPACT Processes window,
now can see the binary counting and , on the board tiny SMD LED (Done) also glows up showing that the FPGA has been configured.
Source Code and Design fileall the source code is available in the github repo WireFrame-FPGA/VerilogHDL-Modules/counter_wireframe,
ModelSim Simmluation , click here to read next post
you can take a look at the video of the test with 3 LEDs, please note you need to connect at pullup ~10K at reset line I/O30 P88, it is under the board in this video .