Sunday, October 11, 2015

WireFrame FPGA Board, Validating counter modules with ModelSim Tutorial

this article is second part of creating  your first design with FPGA and verilogHDL, in particular WireFrame FGPA Board Xilinx XC3S250E board. we are going to use modelSim software From altera which is limited free software available to download from Altera website 

ModelSim Simulation Software From Altera

Creating First Project, LED blinking with Binary Counter , Xilinx ISE Tutorial

First part of this project have created and implemented a basic counter module so that we can blink few leds. now we will verify that counter module with the help of a test-bench module and Altera ModelSim Software, there are many software which you can you to simulate your design none of the component we use are platform dependent.

so lets start , first of all we are going to need a testbench module , testbench module is nothing but a simple verilog module which feeds the inputs to our counter module , monitor the output and ultimately validates that the under test module is working as it should be, to achieve this testbench modules have few extra features or you can call them have extra powers , like you can specify initialization block  and specify time when a instruction will execute due to testbench module never ever get synthesize  , they just run in the simulation software that is all.

lets start writing a test bench ,it will be added to modelsim project as counter_testbench.v

  1. you need a module , 
  2. few reg and wire declaration  for ports of the module under test, 
  3. an instance of the module inter test,
  4. and  a initial block to do one time events, 
  5. and finally a always block to generate clock for the module under test.

`timescale 1ns/1ps  // simmulation happen in picosecond time base ,
                    // we have up scaled it it to ns 
                    // when we say #5 it will mean 5 ns , and when we say #1000 it will 1000ns, 1us

module counter_testbench();

  reg clock_tb,reset;       //mapped with ports of the module under test 
  wire [32:0]out_tb;
  counter t0(reset,clock_tb,out_tb);  //create an instance of the counter module which is under test 
   $monitor("%g,out_tb=%d,reset=%b",$time,out_tb,reset); // these values will be visible in the transcript window at the bottom
  reset=1;  //enable the counter module ,reset is active low input
  #100      // right here we should have (200/5)/2 = 20 in the cout output  value
  reset=0; //reset the timer module for a while
  $stop(); // right here we will have (1000/5)2=100 in the count output

   always #5 clock_tb=~clock_tb;  //generate clock by toggling Clock line ever 5 unit of time


now you we need to create a new project in ModelSim and add

First ModelSim Project

ModelSim starter edition is limited free software you can download it from Altera Website , after installation  , launch modelSim, now got to file menu-> New -> Project 

Specify the project name and project location ,

Create New file or add Existing file ,  you will need only two file for this project , one is testbech another is the actual module under test. (module under test we have already developed in last post)

add existing file to project

compile all the file , see transcript for any error or serious warnings , counter.v is same file as be developed in last post, with Xilinx ISE. counter_testbench.v is the file which we have just written

compilation successful

Start Simulation 

Select the testbech file only!!!

Run all , till it stuck $stop() , see  line number 20 in the test bench source

simulation finish now , you need to go to wave view, though it open automatically , but if it doesn't then go to view menu and select wave  and also sect object window ,

now you need to drag and drop signals from object window to wave window.

Zoom in or out with the buttons in the tool bar so that you can see the whole view 

you can view signal value as tool tip and on the signal it self ,

as you can see we expected 10 value after 200ns , as we are clocking every 10ns (5ns+5ns of always block ) . and soon as reset goes low , the module set to zero.

now after running simulations for 1000 ns we got 100 in the counter output.

result is as be expected, every thing is fine , you can end simulations here or play with test bench for different tests.

Source Code and Design file 

Test in the WireFrame FPGA Board

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