How to build Custom FSBL for Zynq Ultrascale+ FPGA on new Vitis 2024.2

 This post is going to be about how to Create FSBL for Zynq SOC, Using newer version of Vitis 2024.2 . Since Vitis Received update there are changes to well established process of creating FSBL previously with the old version of Wheatus it was very very easy to create FSBL but with the update 2024.2 there are some quite tricks which you need to do to be able to successfully create at FSBL. FSBL is the primary first stage Bootloader which is needed to be able to boot into secondary Bootloader and later on to the target operating system I will be using Xilinx zcu102 as an example board to show you how you can generate custom fsdl for any Xilinx Zynq SoC platform device. you can of course create FSBL for your custom platform.

To create FSBL for a custom platform first of all you need to get started with vivado in vivado you need to create a hardware platform .xsa file and this file is used to create fsp if you are having any standard xilinx Sport for example ZCU102 or ZCU106 then of course you don't need to create a hardware platform file.

Example blow shows you that the part of project has been set up and this is how to export .xsa file

we got our design ready and of course bit stream is also generated you do not necessarily need to generate stream you can export the pre synthesized design as well  now we export

you can choose on this step whether you want a presynthesized design or include bit strain in the exported hardware if you include the stream then this stream can be used to configure the fpga part in the boot first stage itself

by following these steps you must have your .xsa file ready and this file can be used in Vitis to generate a hardware platform which can be used to generate FSBL for that particular hardware platform

we got our .xsa ready we can move to vitis and generate hardware platform and then FSBL with it

On this step you can choose to create the platform on the basis of custom hardware file you created with vivado or you can of course choose default silence development both this step is important on this step you provide necessary input for the FSBL creation and its necessary to pay attention that you choose the correct file and choose the correct platform.

You must uncheck create boot artifacts because we are not looking to "create Boot Artifacts" in this platform

Now our platform have been created FSBL has not yet been created only the platform have been created you must understand there are multiple domains in which code runs so the code which platform which we created does not run in the FSBL domain so we need to create separate at SPL and we will use Xilinx examples FSBL for it you don't necessarily need to write anything . 

Now we have fsbl elf file so we can now create a boot.bin file with this creating boot.bin file requires quite a few of Step you not only need the FSBL you would also need pmu firmware , bl31 File, U boot and also device tree binary  aswell . They need be this exact order 

as you can see we have successfully created our fsbl and now ZCU102 boots