tag:blogger.com,1999:blog-4474580574529252327.post2716067727626945654..comments2024-01-31T08:49:41.013+01:00Comments on Embedded Engineering : Basic Frequency Meter with FPGA , Verilog HDL , WireFrame FPGA Gaurav Singhhttp://www.blogger.com/profile/17880871396648321687noreply@blogger.comBlogger8125tag:blogger.com,1999:blog-4474580574529252327.post-37567743027492255052021-11-07T09:48:16.799+01:002021-11-07T09:48:16.799+01:00Hi Great Work,
I am new to FPGA. Pl let me know h...Hi Great Work,<br /><br />I am new to FPGA. Pl let me know how to send freq [reg [7:0]freq;] value to serial monitor. In verilog I am using an array [ wire [7:0] BIT_ARRAY[7:0] ;] to assign value to array elemnts & sending it to Serial Monitor.Ravi Nhttps://www.blogger.com/profile/14830379518723962568noreply@blogger.comtag:blogger.com,1999:blog-4474580574529252327.post-87560548625388676022019-06-23T09:52:06.238+02:002019-06-23T09:52:06.238+02:00it will work with any FPGA with enough cells to fi...it will work with any FPGA with enough cells to fit model.Gaurav Singhhttps://www.blogger.com/profile/17880871396648321687noreply@blogger.comtag:blogger.com,1999:blog-4474580574529252327.post-28692238956805614732019-06-05T21:39:34.425+02:002019-06-05T21:39:34.425+02:00Could this work with a spartan 3e starter pack fpg...Could this work with a spartan 3e starter pack fpga? Thanks for the post. Alfredhttps://www.blogger.com/profile/06282745743321753699noreply@blogger.comtag:blogger.com,1999:blog-4474580574529252327.post-56481100334922255612018-07-20T04:10:47.345+02:002018-07-20T04:10:47.345+02:00if you cant make a tachometer with FPGA cyclone IV...if you cant make a tachometer with FPGA cyclone IV<br /><br />Anonymoushttps://www.blogger.com/profile/00642420151915887480noreply@blogger.comtag:blogger.com,1999:blog-4474580574529252327.post-72135073310601777992017-01-29T07:46:52.615+01:002017-01-29T07:46:52.615+01:00no, i used my home made Signal Generator no, i used my home made Signal Generator Gaurav Singhhttps://www.blogger.com/profile/17880871396648321687noreply@blogger.comtag:blogger.com,1999:blog-4474580574529252327.post-77949177465255553312017-01-28T14:58:06.717+01:002017-01-28T14:58:06.717+01:00Are you using a 555 timer to generate the waveform...Are you using a 555 timer to generate the waveform and frequency for the FPGA board?Anonymoushttps://www.blogger.com/profile/05229532223862009489noreply@blogger.comtag:blogger.com,1999:blog-4474580574529252327.post-3538278772345956182016-01-29T06:47:50.357+01:002016-01-29T06:47:50.357+01:00certainly it can , but as it has only 8 digit , ei...certainly it can , but as it has only 8 digit , either you add one more digit or you have resolution of 10Hz instead 1Hz. in both case little modification to verilog code is required. Gaurav Singhhttps://www.blogger.com/profile/17880871396648321687noreply@blogger.comtag:blogger.com,1999:blog-4474580574529252327.post-67418811000493925042016-01-29T01:41:55.397+01:002016-01-29T01:41:55.397+01:00What would be the maximum frequency this could det...What would be the maximum frequency this could detect? Would it work up to 125MHz?GIhttps://www.blogger.com/profile/17506673717977357930noreply@blogger.com